MOS Transistor
MOS transistors are very complex devices to model completely.
Today, most MOS models try to fit the behavior of all possible devices in a process at once:
for all combinations of width w and
length l.
The models presented here are less ambitious and, because of their simplicity,
better suited for analog design.
First, we have the “classic” level 1 model as proposed by Shichman and Hodges:
The saturation voltage Vsat is calculated as an auxiliary variable,
because it features in the conditional that separates the linear and saturated regions.
It is not absolutely required, but we find that it does improve the numerical stability of the problem.
The level 2 model is the next step-up. A number of additional geometric and physical effects are taken into account, in order to extend the model to smaller gate lengths (down to approximately 1 μm). Still huge in today's nanoscale world, of course.
Below is measurement data from a real w = 50μm and
l = 1μm n-channel device.